LDMOS transistor structures are widely used as semiconductor devices for many types of transistor applications such as high voltage MOS field effect transistors. An LDMOS transistor comprises a lightly doped drain region to enhance the breakdown voltage. LDMOS transistors comprise, thus, a higher on resistance due to the lightly doped region within the drain.
FIG. 1 shows a typical power LDMOS transistor. A wafer comprises, for example, a p substrate 13 on top of which an epitaxial layer 1 is deposited. This layer 1 includes n conductivity type areas 2, 4 and 15 implanted into the surface to provide a source and drain region, respectively. The epitaxial layer 1 is usually covered with an insulating dielectric layer 7 such as silicon oxide in which a polysilicium gate 8 is arranged to cover the channel between the drain 4, 15 and source 2. The drain in this exemplary LDMOS transistor comprises a first region 15 which is n+ doped and which comprises a connection to a drain electrode 12 arranged above that region 15 through a window in the insulator layer 7. This n+ region is surrounded by a lighter doped n− region 4 that extends until under gate 8 to define a channel between the source and the drain region. On the source side of this transistor a p+ doped sinker 14 is provided which extends from the surface of the epitaxial layer 1 down to the substrate to provide for a backside source contact. Contact 11 connects the source region 2 with the sinker 14.
The interrelation between breakdown voltage and on-resistance relates to the maximum electric field defined by the pn-junction which needs to stay below the critical electric field for the semiconductor to avoid breakdown. This maximum electrical field is defined by the doping level of, for example, the n− doped drain in a nmos field effect transistor. Furthermore, in applications in which the transistor is most of the time driven to conduct, the long on-state can lead to substantial hot carrier injection resulting in DC parametric drift. This is a very common issue with LDMOS transistor structures because the n-implant doses are increased in LDD transistors to lower the on-resistance, thus, resulting an higher junction electrical field and hot electron injection over time.